1. Technical Field
The present invention generally relates to computer systems and in particular to branch prediction tracking mechanisms. Still more particularly, the present invention relates to global history vectors utilized with branch prediction and folding techniques for optimizing timing.
2. Description of the Related Art
Branch prediction, and in particular global branch prediction, is known in the art. Global branch prediction involves making a branch prediction based on the path of execution, i.e., the history of the last few branches to have been executed. Global branch prediction may implement a special shift-register storing a bit-vector, referred to as a “global history vector,” that represents the recent path of execution. The global history vector may store n bits of data, with each bit of data associated with a group of instructions. The position of a bit in the global history vector corresponds to how recently the associated group of instructions was fetched. For example, the least significant bit in the global history vector may represent the most recent fetch and the nth most significant bit may represent n fetches ago. If the group of instructions fetched contained a branch instruction whose branch was taken, then a “1” may be indicated in the global history vector corresponding to that group of instructions. Otherwise, a “0” may be indicated in the global history vector. That is, a “0” may be indicated in the global history vector if the corresponding group of instructions did not contain a branch instruction or if the group of instructions did contain one or more conditional branch instructions and each of these branches were not taken. Upon each successive fetch of a group of instructions, the global history vector is updated by shifting in an appropriate “1” or “0” and discarding the oldest bit.
The GHV is generally exclusive ORed with the Instruction Fetch Address Register (IFAR), and the resulting address is used to address a portion of the Branch History Tables (BHT). The calculation of both GHV and the IFAR is generally critical to cycle time, which is a key measure of processor efficiency. Also, conventional use of the GHV requires the GHV be folded along upper and lower bits before XORing the folded GHV values with the IFAR. Precious system resources and time are utilized as GHV address and IFAR address are individually calculated. Also, a measurable amount of scarce system resources and time are required when the addresses of the GHV and IFAR are exclusive ORed together.